Designing Network On-Chip Architectures in the Nanoscale Era

A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs—consistently focusing on topics most pertinent to real-world NoC designers. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues. They also explore the latest trends, such as vertical integration and variation-tolerant design.